This application claims the priority benefit of Taiwan application serial no. 91102059, filed Feb. 6, 2002.
1. Field of Invention
The present invention relates to a pixel structure. More particularly, the present invention relates to a pixel structure having a data line with an alignment mark underneath.
2. Description of Related Art
The rapid progress in multi-media communication is largely a consequence of technological advances in the manufacturing of semiconductor and display devices. In the past, cathode ray tubes (CRTs) are the principle types of display devices in the market due to stable quality and relative low cost. However, bulkiness, weight and power consumption restricts the CRT to a desktop terminal/display type of environment. In recent years, thin film transistor liquid crystal display (TFT-LCD) has gradually replaced CRT as a dominant display device. A TFT-LCD not only provides high-quality picture image and uses very little power, the display device is light, compact and radiation free as well.
FIG. 1 is a schematic top view of a conventional thin film transistor array having an alignment mark thereon. In general, a thin film transistor array is formed on a sheet of transparent substrate 100. The transparent substrate 100 is divided into a plurality of blocks 102. Each block 102 includes a pixel array 104. Each pixel array 104 comprises a plurality of pixels with each pixel falling on a pixel point ordered into an array. In addition, a pair of alignment marks 106 is formed on the opposite corner of the pixel array 104 in each block 102. Each alignment mark 104 is constructed from a first metallic layer 106a and a second metallic layer 106b stacking on top of the first metallic layer 106a. 
FIG. 2 is a schematic top view of a conventional pixel structure. As shown in FIG. 2, pixel units are normally formed over a transparent substrate 200. Each pixel unit comprises of a thin film transistor 202, a pixel electrode 204 corresponding to the thin film transistor 202, a scan line 206 and a data line 208. The thin film transistor 202 further comprises a gate electrode 202a, a channel layer 202b and source/drain terminals 202c. The scan line 206 and the gate electrode 202a of the thin film transistor 202 are electrically connected. The pixel electrode 204 and the data line 208 are electrically connected to the respective source/drain terminals 202c. 
As shown in FIG. 2, the fabrication of an array of pixel units 200 involves many steps. Such steps include forming the gate electrode 202a and the scan line 206, the channel layer 202b, the source/drain terminals 202c and the data line 208, the source/drain (S/D) contact 210 and the pixel electrode 204. Hence, the alignment of photomask in each step is critical. Any mis-alignment of the photomask may lead to a shift in position of the channel layer 202b within the thin film transistor 202 or a non-symmetrical layout of the source drain terminals 202c on each side of the channel layer 202b. 
The first metallic layer 106a and the gate electrode 202a of the thin film transistor 202 are formed using the same photomask. Similarly, the second metallic layer 106b and the source/drain terminals 202c of the thin film transistor 202 are formed using the same photomask. Hence, by observing the relative stacking position of the first metallic layer 106a and the second metallic layer 106b, any mis-alignment between the two photomasks can be determined and non-symmetrical distribution of the source/drain terminals 202c on each side of the channel layer 202b can be prevented. Since the alignment mark 106 only points to any alignment problems between the gate electrode 202a and the source/drain terminals 202c, the alignment mark 106 is unable to prevent any incorrect positioning of the channel layer 202b. 
Accordingly, one object of the present invention is to provide a pixel structure that provides a better alignment between the source/drain terminal and the gate electrode within each pixel unit.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a pixel structure on a transparent substrate. The pixel structure mainly includes a first conductive layer, a first dielectric layer, a channel layer, a second conductive layer, a second dielectric layer and a pixel electrode. The first conductive layer is formed over the transparent substrate. The first conductive layer further includes a scan line, a gate electrode and an alignment mark. The first dielectric layer is formed over the transparent substrate and covers the first conductive layer. The channel layer is formed over the first dielectric layer above the gate electrode. The second conductive layer is formed over the first dielectric layer. The second conductive layer further includes a data line and a source/drain terminal. The second dielectric layer is formed over the first dielectric layer and covers the second conductive layer. The pixel electrode is formed over the second dielectric layer. The alignment mark is formed beneath the data line.
According to this invention, the gate electrode, the channel layer and the source/drain terminals together constitute a thin film transistor. In addition, the gate electrode connects electrically with the scan line. Similarly, the pixel electrode and the data line connect electrically with the source/drain terminals. The scan line extends in a direction perpendicular to the data line. The alignment mark has a longitudinal profile and extends in a direction parallel to the data line. Furthermore, width of the alignment mark is equal to or smaller than the data line.
This invention also provides a thin film transistor array that includes a transparent substrate, a first conductive layer, a first dielectric layer, a plurality of channel layers, a second conductive layer, a second dielectric layer and a plurality of pixel electrodes. The first conductive layer is formed over the transparent substrate. The first conductive layer further includes a plurality of scan lines, a plurality of gate electrodes and a plurality of alignment marks. The first dielectric layer is formed over the transparent substrate covering the first conductive layer. The channel layers are formed on the first dielectric layer above various gate electrodes. The second conductive layer is formed over the first dielectric layer. The second conductive layer further includes a plurality of data lines and a plurality of source/drain terminals. The second dielectric layer is formed over the first dielectric layer covering the second conductive layer. The pixel electrodes are formed over the second dielectric layer. The alignment marks are positioned beneath the data lines.
According to this invention, the gate electrodes, the channel layers and the source/drain terminals together constitute a thin film transistor array. In addition, each gate electrode connects electrically with a corresponding scan line. Similarly, each set of pixel electrode and data line connects electrically with a corresponding pair of source/drain terminals. The scan lines extend in a direction perpendicular to the data lines. The alignment marks have a longitudinal profile and extend in a direction parallel to the data lines. Furthermore, width of the alignment marks is equal to or smaller than the data lines.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.